Sentence examples for cache instructions from inspiring English sources

Both cores do not cache instructions.

Moreover, for hierarchies that have a unified second-level cache (instructions and data), this number can total thousands of configurations, owing to the interdependence between data and instructions at the second level [10].

The method cache M$ caches instructions of a full method/function.

A function-based dynamic instruction scratchpad (D-ISP), an instruction cache, and static instruction scratchpads using basic-block-based and function-based assignment algorithms are compared.

Oracle Database uses memory as a number of buffers to cache both instructions and data.

The results show that with the exception of the input data set, the working set fits into an 8-Kbyte data cache; the instruction working set also fits into an 8-Kbyte instrucache cache.

Therefore, split caches for instructions and data are used, to best utilize the accessing pattern.

Cache state Instruction Memory Youngest Oldest a.v = 123; store a.v a.v — — — b.v = 456; store b.v b.v a.v — — c.v = b.v; load b.v b.v a.v — —   store c.v c.v b.v a.v — d.v = b.v; load b.v b.v c.v a.v —   store d.v d.v b.v c.v a.v b.v = a.v; load a.v a.v d.v b.v c.v   store b.v b.v a.v d.v c.v.

This paper proposes a new instruction cache architecture, named Partitioned Power-aware instruction cache (PP-cache), for reducing dynamic energy consumption in the instruction cache by partitioning it to small sub-caches.

The interference between the folding unit, the instruction buffer, the instruction cache, the stack buffer, the data cache, and the memory interface causes complications in modeling picoJava for WCET analysis.

The instruction compression mechanism used to solve the drawbacks of traditional very long instruction word (VLIW) architectures often leads to poor code density in the instruction cache, which causes the irregular lengths of long instructions to cross the different cache line.