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Results are normalized to the number of reads and writes without bypassing with TD.
In this figure, we display the number of clock cycles normalized to the worst case without software bypassing with top-down scheduler for (a) gsm and (b) motion.
The addition of read and write ports improves the cycle count to a lesser extent than software bypassing, with exception of the gsm benchmark, where bypassing with a single register file with a single read and single write port does not improve performance as much as the addition of read and write ports or more register files.
Figure 14a,b shows the breakdown of the register consumption of register files for mips and motion benchmarks, with a visible effect of dramatic reduction in register file reads and writes observed in Figure 8b causing a significant difference in energy between software bypassing with top-down scheduler and software bypassing with bottom-up scheduler in the case of motion.
In this figure, we display the relative energy without bypassing in the left side and the relative energy with bypassing in the right side, normalized to the case with fully connected architectures without software bypassing with top-down scheduler.
In this figure, we display the number of dynamic register file reads and writes after the application of software bypassing normalized to the worst case without software bypassing with top-down scheduler for (a) mips and (b) motion.
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Justyna Jupowicz-Kozak
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