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Therefore, analysis of the effects on other nodes, caused by the soft errors occurring at each individual node is an essential step for VLSI logic circuit design.
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The soft errors occurred by helium ions were induced by a floating body effect due to generated excess charge carriers in the channel regions.
With continuous scaling down of the semiconductor technology, the soft errors induced by energetic particles have become an increasing challenge in designing current and next-generation reliable microprocessors.
The soft errors, occurred by oxygen ions with energies at and below 12.5 MeV, were induced by a floating body effect due to the generated excess charge carriers in the channel regions and those with energies at and above 13.0 MeV were induced by both the floating body effect and generated excess carriers.
Recently, FT performance has become more important, partly due to the fact that the soft errors caused by transient faults are an unavoidable concern in very large-scale integration (VLSI) technology, whose dimension is approaching the nanoscale (Mahdiani et al., 2012).
Simulation results show that our proposed method can reduce the soft error vulnerabilities by 14%26%%.
The soft error occurred by oxygen ion irradiation with energies at and above 10.5 MeV in the SOI SRAM.
For instance for MLC PRAM, Xu and Zhang[11] proposed a hybrid technique that first reduced the soft error rate by adjusting the threshold resistance and then used BCH or LDPC codes on large code words to improve the reliability with high storage efficiency.
Furthermore, we propose to maximize the access on the soft error invulnerable dies by dynamically moving data blocks among different dies, thereby achieving further performance and energy efficiency improvement.
The soft error rate in multicore systems increases by the trend in the transistor sizes and the reduction of the voltage of the transistors.
By adjusting the cell orientations of the quenching cells in the layout, the soft error vulnerabilities could be further reduced.
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