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The data processing in the datapath is controlled by control signals decoded by the instruction decoder in the control path.
Two general purpose register files, Register File 1 and Register File 2, in Figure 3 are used with a register input generator controlled by the instruction decoder directly.
The choice of the maximum correlation length was based on the required performance in 802.16e and 3GPP-LTE release 8. Inputs to the memory system is connected to a Memory Input Generator in Figure 3, which is controlled by the instruction decoder.
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Shifters included with the engine core are not general purpose shifters that accept arbitrary inputs; they are used only in the execution of the iterative CORDIC algorithm and are controlled by a counter attached with the instruction decoder.
Two parts of hardware can be found in a control path: the instruction flow controller and the instruction decoder.
The ROM takes its address directly from the instruction decoder with an internal counter for its address only.
Four IC signals are connected directly with the instruction decoder and used for acknowledgment about a certain event.
The CU is connected to the output of a CU input generator and controlled directly by the instruction decoder (ID) with a 26-bit control vector, which identifies the working operation and the used elements inside the CU. Figure 4 shows the internal design of CU.
The first group of neurons (pool 1 in Figure 1A) contributed to the decoder's heading report (decoding weight = 1), while responses from the other group (pool 2) were ignored by the decoder (decoding weight = 0).
The AND NOR decoder dissipates between 15% less and 20% more (6% more on average) energy than dissipated by the NOR decoder.
Access to specific modules is provided by the address decoder.
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