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Besides, to prevent SiC fibers from detrimental reactions with MoSi2 during sintering, a ZrB2-based buffer layer is sandwiched between the fiber-rich bulk and the outer MoSi2-containing scale.
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Typically for this device structure, the perovskite layer is sandwiched between the anode and cathode buffer layers to form a p-i-n-layered energy level alignment.
The graphene layer is sandwiched between the silicon and silica.
The K layer is sandwiched between the SiO4 layers in its cleavage planes.
The SiNWs have core shell structures where the Er-crystalline layer is sandwiched between silica layers.
For ECM devices, resistive layer is sandwiched between an inert electrode and an active electrode.
Typically, the PS layer is sandwiched between the c-Si substrate and a metallic contact.
In the former case, a dielectric layer is sandwiched between a metal layer and the prism.
In the latter case, the metal layer is sandwiched between a prism and the sensing medium.
19 The bottom part of the stacking has a per-layer doping of n1 = 1.07 × 10cm−2 and the stoichiometry of stage-1 FeCl3 graphite intercalation compounds (i.e. where each graphene layer is sandwiched by two FeCl3 layers).
A 1.3-μ m AlN piezo layer was sandwiched between AlCu/W electrodes.
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