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The role for an external Sn supply from the buffer layer is discussed based on the experimental results.
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The influences of substrate temperature and oxygen partial pressure on the microstructure and surface morphology of LZO buffer layers were discussed.
The mechanisms of the improved corrosion current density by the Ta coating and the enhancement of mechanical bonding of the Ta coating by a Ti buffer layer are further discussed.
Will the contact property of interfaces between active layer droplets and cathode buffer layers be changed when the buffer layer is modified?
When an aluminum buffer layer is deposited on electrically conductive carbon paper, high yield CNTs can be achieved while no CNTs can be observed without this buffer layer.
A functionally graded piezoelectric material (FGPM) buffer layer is in between the upper layer and the substrate.
Furthermore, the Si0.5Ge0.5 buffer layer is also helpful for the enhancement of performance.
The thickness-insensitive PDINO cathode buffer layer is beneficial to higher short circuit current density.
An additional tunneling factor which characterises the tunneling effect of buffer layer is introduced.
Through a space electric field concentrated effect, the SCLC conduction of the Zr:SiO2 RRAM devices using the porous SiO2 buffer layer was explained and discussed by the COMSOL Multiphysics simulation model.
Oxide buffer layer was pre-sputtered using RF sputtering technique.
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