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This technique can be used for both combinational and sequential circuits.
The presented circuits belong to different categories, covering both combinational and sequential circuits.
Some PLDs are made to perform only combinational logic functions while others can perform both combinational and sequential logic functions.
A parallel SER (soft error rate) evaluation framework ASSET-VLG was developed to analyze the SER of both combinational and sequential standard cell circuits.
The chapter also identifies the PLDs that are capable of performing both combinational and sequential logic functions; however, it limits the exemplar applications to combinational logic design.
In this paper, we propose a fast simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like selecting the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli.
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This paper deals with the QCA implementation of some of these combinational and sequential circuits.
We propose and analyze different combinational and sequential decimal left shifter architectures for binary numbers.
Therefore, numerous combinational and sequential circuits have been redesigned and implemented using this new technology.
Logic level optimization attempts to optimize the power of the switching activity of combinational and sequential circuits.
In this paper we have used an evolutionary algorithm to design some combinational and sequential logic circuits.
More suggestions(12)
both monolingual and sequential
both content and sequential
both temporal and sequential
both parallel and sequential
both expressional and sequential
both structural and sequential
both spontaneous and sequential
both concurrent and sequential
both random and sequential
both equibiaxial and sequential
both tonic and sequential
both simultaneous and sequential
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