As an essential low-voltage circuit, a triple pumping scheme is proposed to generate a stable boosted voltage whose level exceeds over twice the supply voltage and which is required for the boosted word-line bias.
In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while another bitline is connected to a boosted voltage.
Figure 23 Power and energy consumption for different values of boosted voltage and write pulse width.
For instance, when pulse width is 30 ns, write-1 BER = 0.25 × 10 2 when the boosted voltage is 1.1 V, whereas write-1 BER = 0.4 × 10 4 when the boosted voltage is 1.3 V. Figure 22 BER versus write pulse duration for different values of SL voltage.
For BER = 10 5, we consider the following combinations of write pulse widths and boosted voltages: (60 ns, 0.9 V), (42 ns, 1.1 V), (31 ns, 1.3 V), and (25 ns, 1.5 V).
Figure21 illustrates the latency distribution of write-1 operation when access transistor size is W/L = 4, BL is set to zero and SL varied from 0.9 (nominal) to 1.5 V. We see that boosting SL voltage level over nominal voltage level reduces the average latency and variation of the write-1 operation.
Therefore, dc-dc converters are able to improve the steady state performance of TEG system as well as boosting the voltage to the desired level, hence improving the overall performance of TEG system.
Similarly for STT-RAM, the hard error rate can be reduced by tuning the W/L ratios of the access transistors, boosting the voltage, and adjusting the write pulse width.
Depending on the opsin used, shining light on the cell either lowers the voltage and silences neuron firing, or boosts voltage and provokes the cell to generate an electrical impulse.
Inverting Op-amp is used to boost the voltage from mV to voltage range.
