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It was revealed that there is a correlation between the defect density and the grain size.
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The analysis is based on the recovery curves of the G/D ratio and there is no need to assume a specific functional form between the G/D ratio and the defect density.
First, optimal patterning can reduce the defect density due to the lattice mismatch between the sapphire substrate and the nitride layer [49].
Time between pre-treatment and coating process is of important influence on the defect density as our investigation shows.
The defects identified were limited to "high-impact" and "medium-impact" from Coverity's Static Analysis scanning suite, which include things like Null Pointer Dereferences, Uninitialized Variables, Memory Corruption, Error Handling, Illegal Memory Access, etc. Breaking down the defect density within each of the software components, the kernel has a higher defect density.
Post-HPT, Si-QDSL defect density (1.1 × 1019 cm-3) clearly reduced compared with the defect density before HPT.
Interrupting the deposition process did not decrease the defect density.
Therefore, to make a more direct comparison we looked at the defect density of proprietary code against open source codebases of similar size.
For the 400°C treatment, defect density decreases to 3.7 × 1017 cm-3, which is comparable with the defect density of an a-SiC film.
However, controlling the defect density of the 3DGN during the chemical vapor deposition process is complex.
The electric process can bring impacts about the defect density in the insulator/semiconductor [3, 14].
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