On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements.
A feedforwarding architecture is employed to decrease the latency between processing elements, in parallel with the word-based accumulation units, which are also pipelined.
In practice, the communication is realized as data messages transmitted between real-time operating system (RTOS) threads or between processing elements over an on-chip communication network.
Thus, the application developer does not need to care about where specific computational services will be located at run time (he can, however, provide constraints if needed, such as when low latency is required between processing elements, e.g., to compute a correlation between data streams).
Systems based on artificial neural networks have high computational rates due to the use of a massive number of simple processing elements and the high degree of connectivity between these elements.
A multiprocessor is composed of processing elements and memory elements with an interconnection network.
A typical MPSoC is a heterogeneous multiprocessor there may be several different types of PEs, the memory system may be heterogeneously distributed around the machine, and the interconnection network between the processing elements (PEs) and the memory may also be heterogeneous.
This knowledge is modeled as the connections between the processing elements (artificial neurons) and the adaptive weights of each of these connections.
The control system synthesis is based on Hardware Petri nets that are composed of two kinds of processing elements (Places and Transitions) and data flow path between them.
Contour integration is a fundamental mid-level stage in visual processing that involves cooperative interactions between local processing elements, with contributions to higher-level tasks such as perceptual grouping, image segmentation, and object recognition (Kovacs et al., 1999; Kovacs et al., 2000).
