The resulting capacity regions show the tradeoff between the performance improvement and the requirement for BS cooperation, signal processing complexity, and channel state information at the transmitter (CSIT).
Hence, it does not introduce additional processing complexity and delay.
The comparison of the achievable rates by the different proposed cooperative schemes showed a trade-off between performance improvement and the requirement for BS cooperation, signal-processing complexity, and channel state information (CSI) knowledge.
According to our interpretation, for common and typical words, processing complexity C is low and, thus, P1 amplitude is small.
This work contains a detailed discussion of tradeoffs between performance improvement, requirement of channel knowledge, and processing complexity.
Throughout the paper we explore the design space at different levels (algorithm, arithmetic accuracy, architecture, technology) to achieve the best trade-off between processing performance, hardware complexity and power consumption.
Such a processing scheme provides a suitable compromise between computational complexity and latency, and enables to achieve a suitable time and frequency resolution.
The proposed architecture is designed and implemented in FPGA to illustrate the relationship between hardware complexity and execution throughput of hyperspectral image processing for target detection.
Links between neural complexity and information have been identified [3], [4], and recent work aims at modelling the information processing throughout the perception-action loop of agents [5] [11].
