Sentence examples for benchmark circuits show that from inspiring English sources

Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.

Experiments on different HLSynth92 benchmark circuits show that the test generation time is greatly improved using HLDDs, thus, large circuits can be easily handled.

The results of experiments carried out for the chosen benchmark circuits show that the achieved reduction of power consumption varies from 4 to 52%.

Experimental results on the larger ISCAS'89 and ITC'99 benchmark circuits show that the holistic strategy can reduce test power in shift cycles and capture cycles significantly under the constraint of certain compression ratio.

Simulation results on benchmark circuits show that our approach obtains a significant speedup over other existing methods, especially when the reliability evaluation is repetitively needed for a same circuit in order to provide the reliability improvement for reliability-driven design applications.

The experimental results on benchmark circuits show that compared to the results produced by the best known ADB allocation algorithm, our proposed algorithm uses, on average under 30 50 ps clock skew bound, 13.5% and 15.8% fewer numbers of ADBs for continuous and discrete ADB delays, respectively.

Experiments on ISCAS׳85 and ISCAS׳89 benchmark circuits show the evaluation time ranges from 0.5 ms to 2.16 s without previous memory explosion problem.

Experimental results over various architectural level benchmark integrated circuits show that average leakage optimization of 90% can be obtained.

The application of the proposed technique to ISCAS-85 C17 benchmark circuit shows 20% reduction in the leakage power as compared to conventional gate-level dual-Vth assignment technique.

Experimental results are given for a number of 90 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty.

Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.