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For the sequential implementation on FPGA platform, the proposed hardware architecture has been implemented on a Xilinx Virtex-6 ML605 FPGA.
The framework has been implemented on a GPGPU platform.
The design has been implemented on a Virtex 1000E FPGA.
The system has been implemented on a PalmPilot.
The project has been implemented on a Xilinx Virtex 5 FPGA.
Both channel emulators have been implemented on a Virtex IV FPGA (XC4VSX35-10FF668).
The proposed framework has been implemented on a typical 11 kV overhead distribution feeder.
The proposed product has been implemented on a commercial parametric feature based solid modeling system.
The proposed control strategy has been implemented on a flexible spacecraft.
It has been implemented on a PC architecture, connected with two different types of waveform digitizers.
This method has been implemented on a case study and has been evaluated qualitatively and quantitatively.
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