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Athalye et al. [7] presented generic architectures for the implementation of the Sequential Importance Resampling Filter (SIRF).
Programmable architectures for the implementation of these kernels allow the utilization of different sequence lengths as well as the change between the computation of correlation or autocorrelation functions, in order to support many different standards.
In this paper, we explore alternative architectures for the implementation of hash algorithms of the secure hash standards SHA-256 and SHA-512 on FPGAs and study their area-performance trade-offs.
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Figure 6 shows the software architecture for the implementation of the M2M service platform.
A specific architecture for the implementation of the integrated RFID and cellular localization system is proposed in Fig. 4.
This paper presents the first crossbar based nanoscale computing platform (nano-architecture) for the implementation of encryption algorithms.
We have discussed briefly the client server architecture for the implementation of our system.
In [8], for example, an architecture for a single-chip JPEG codec is described, in [9, 10], an architecture for VLSI implementation, and in [11, 12], another architecture for the implementation in FPGA.
Section 3 describes the proposed hardware architecture for the implementation of an OFDMA-TDD PHY compliant with the mobile-WiMAX standard.
Moreover, a cloud-based architecture for the implementation of this strategy is proposed, as an attempt to deliver adaptation as a service.
A high performance digital architecture for the implementation of a non-linear image enhancement technique is proposed in this paper.
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Justyna Jupowicz-Kozak
CEO of Professional Science Editing for Scientists @ prosciediting.com