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Moreover, several of those crosscutting concerns are best described at the architecture level.
System modeling is thus performed primarily at the logical architecture level.
Our model can be used for initial exploration of the design space at the architecture level.
We present a new architecture level unified reliability evaluation methodology for chip multiprocessors (CMPs).
Based on this assumption, we propose a software power modeling method at architecture level.
In addition, the usage of the FS-graph supports aspect-oriented programming at the architecture level.
Similar(16)
We also summarize common representations of the design space and compare current system and micro-architecture level design frameworks.
Both algorithms are scheduled statically at the micro-architecture level.
Our work is similar to this kind of simulator because our objective is to evaluate the power-performance behaviour of a micro-architecture level design abstraction.
On the other hand, micro-architecture level simulators provide the power estimation across cycles and these are used in modern processors.
At the early stage of the processor design, various levels of simulators can be used to estimate the power and performance such as transistor level, system level, instruction level, and micro-architecture level simulators.
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