Sentence examples for architecture delay from inspiring English sources

Since its original conception as a space-oriented communications architecture, Delay Tolerant Networking (DTN) has been generalized to address issues in terrestrial networks as well.

Due to the shared bus in the Xeon's architecture, delays were greater than the DirectConnect approach of the Opteron, and thus the difference in the stall time.

In WLANs that have an RoF-based architecture, delays longer than one half of a slot time cause unexpected frame collision patterns and increase the probability of frame collisions when the WLAN operates using a conventional MAC protocol.

In the proposed architecture ECC delay is moved to the non-critical path of the process by directly comparing the retrieved tag with the incoming new information which is encoded as well, thus reducing circuit complexity.

An associated cross-layer architecture for delay-tolerant WSNs was also proposed.

Our data suggest that in the postischemic brain PKC δ co-localizes with PLSCR3 in mitochondria and this event might influence the mitochondrial membranes architecture and delayed neurons degeneration.

Instead, defects in NMJ maturation were reported in these SMA mouse models, with abnormalities in pre-synaptic architecture and delayed maturation of the post-synaptic motor endplate [17], [18], [20] [22].

The To miR171 over-expressing plants (OE171) showed a pleiotropic phenotype with altered shoot architecture and delayed flowering.

This model can well describe many practical architectures of delayed neural networks, which is generalization of some additive delayed neural networks such as delayed Hopfied neural networks and delayed cellular neural networks, under a time-varying environment, particularly when the network parameters and input stimuli are varied periodically with time.

The model can well describe many practical architectures of delayed neural networks, which is generalization of some existing neural networks under a time-varying environment.

Last, we demonstrate the effectiveness of our architecture for abnormal delay detection using experiments in a testbed.