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In our architecture, each sensor node executing the application under test is paired with a modified sensor node called the control node.
Patterns can also be set up to create test situations that rarely happen in the real world, but under which the user wants to investigate the reaction of the protocol or application under test.
We present an architecture for a system that utilizes sensor nodes to provide the required stimuli and can exercise control over other sensor nodes that are executing the application under test.
A case study was conducted using this method and the observations showed that the automation architecture was resilient to change while increasing the test coverage, the depth of testing, and the overall quality of the application under test.
Test analysis is the activity to refine Application Under Test (AUT) into proper size that test design techniques can be applied to.
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For most applications under test, the SmartCell can be dynamically reconfigured in less than 1 microsecond, which is much faster than the fine-grained FPGA reconfigurations.
Once you have test suites in conformance with programs implemented in both paradigms, the quality of such suited in termos of code coverage may vary depending on the size and characteristics of the applications under testing.
Previous hardware/software co-design frameworks have only considered the design-under-test (DUT) application for hardware components.
For testing the application under varying network loads, straightforward techniques can be applied to alter the originally captured traffic trace.
Once your application is built, test, and then test more.
The methodology integrates statistical fault-injection testing with the application of on-line, model-based performance monitoring of the embedded control system under test.
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