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Figure 8 Control algorithm diagram of FAST protocol.

Through simulating three-phase voltage of electronic power system, this paper completes voltage fluctuation rate monitor of electronic power system and electronic power quality judgment, as well as verifies accuracy of algorithm diagram procedure.

In FAST, a route discovery (RD) process is initiated when a source node needs to determine a route for destination node, control algorithm diagram of FAST protocol is illustrated in Figure 8.

Through SOC loop control, SC SOC value is kept in the range from 0.25 to 1. Open image in new window Fig. 7 Control algorithm diagram of wayside SC storage system.

Fig. 3 Battery parameters/SOC co-estimation algorithm block diagram.

The algorithm block diagram is shown in Fig. 4.

However for this purpose, the particles called as power of pilot tones are initialized at random values between 0 and 1. Figure 2 PSO algorithm flow diagram.

The algorithm flow diagram for this multi-step procedure is shown in Figure 1.

The software code, its architecture, input and output files, the solution algorithm, flow diagrams and source programs are described in detail.

The study algorithm is diagrammed in Additional file 2. The research team will carry out the analysis of prescription adequacy.

Next, to conveniently illustrate the proposed JVSS algorithm, the state diagram in Figure 2(a) can also be expressed by the trellis diagram in Figure 2(c).