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Our best implementation of a one-level two-dimensional discrete wavelet transform achieves a throughput of 66.8 megapixels per second using 7726 logic elements.
The proposed decoder has been implemented on a Xilinx FPGA suitable for WiMAX application and achieves a throughput of 548 Mbps.
With this version, the computation of the optical flow achieves a throughput of 45 images per second with 502×288 pixel images.
Anyway, with this parallelization scheme, the computation of the optical flow achieves a throughput of 30 images per second with 502×288 pixel images.
Our implementation operating at 10 MHz achieves a throughput of greater than 700 Mbps, which is several times higher than previous implementations.
We provide experimental results on an Altera Stratix II FPGA demonstrating that the processor computes a single scalar multiplication on average in 11.71μs and achieves a throughput of 235,550 scalar multiplications per second on NIST K-163.
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Cable modems achieve a throughput of several megabits per second (Mbps; million bits per second).
We can see that all the three approaches achieve a throughput of 100% in all cases.
The problem with IP lookup is that of achieving a throughput of more than 100 gigabits per second.
The design of the dividers is fully pipelined, and they can achieve a throughput of one division per clock cycle.
The results showed that the proposed method achieved a throughput of 2.4 Gbit/s while processing the traffic.
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