We employ the above techniques in designing a 7-bit SAR ADC, in which 3 bits are resolved with time-comparator blocks and 4 bits are resolved with a voltage-comparator.
The demodulator utilizes a new ultra low power envelope amplifier that removes the need for any voltage comparator or Schmitt trigger circuit.
The measurement itself relies on a 1-bit ADC (i.e. a single voltage comparator), and the digitalization of the sensor's response is achieved by a digital clock, which is very effective in terms of extra-power consumption, silicon area and design time, if monolithically integrated with the sensor.
The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented.
The structure and gain of the pre-amplifier are optimized, and the ultra-high-speed voltage comparator is realized.
A signal processing circuit composed of charge amplifier, high-pass filter, absolute value amplifier, envelope detector and voltage comparator in series was designed to detect grain impact signal.
The electrostatic AC-DC voltage comparator for precise voltage measurement in voltage range of 100 1000 V and frequency range of 20 100,000 Hz was designed.
The Front-end circuits include the sensor's low-voltage drive circuit, preamplifier circuit, filter circuit, the voltage comparator circuit and the signal isolation circuit.
