The phrase "a high level synthesis" is correct and usable in written English.
It can be used in contexts related to engineering, computer science, or design, where it refers to the process of creating a high-level representation of a system or design.
Example: "The team focused on a high level synthesis of the project requirements to ensure all aspects were considered before implementation."
Alternatives: "an advanced synthesis" or "a comprehensive synthesis".
A high level synthesis approach was presented in [15] for generating the embedded processor arrays for matrix algorithms based on the polytope model.
Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design.
Optimal DSP blocks such as digital filter design is a high level synthesis problem which includes optimally mapping digital filter specifications on to FPGA (Field Programmable Gate Array) architecture.
We extend the concept of design space to include testability and show how this enhanced design space can be used by a high-level synthesis tool.
The neural network is based on the Izhikevich model and mapped to a CPU-FPGA hybrid device using a high-level synthesis flow.
This review provides a high-level synthesis of significant recent advances in artificial neural network research, as well as multi-disciplinary concepts connected to the far-reaching goal of obtaining intelligent systems.
A high-level synthesis tool bridges the gap between an algorithmic description of a design and its structural implementation at the register transfer level, and is the next natural step in design automation, succeeding logic synthesis.
We rely on dataflow modelling of the algorithm and we use a high-level synthesis tool in order to specify the local dataflows of our Processing Element (PE), by describing in C language inter-PE communication, fine scheduling of the successive convolutions, and memory distribution and bandwidth.
The degree of conditional hardware reuse achieved after a high-level synthesis process depends on two factors: the number of mutually exclusive (mutex) operations pairs that an algorithm can detect and the description style used by the designer when specifying the system.
To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs.
The combination of the logic model and proposition development and testing appears to have been an effective and transparent way to arrive at a high-level synthesis of the data, which was the goal of this study.
