Sentence examples for a digital phase from inspiring English sources

Since the system is not unconditionally stable, a digital phase lag compensator is designed to guarantee the stability for larger feedback gains.

The in-loop measurement done with a digital phase detector with a 4-bit capture range is shown in blue, the out-of-loop measurement performed with an analogue phase detector in red.

The offset correction process is achieved via a digital phase locked loop (PLL) and a direct digital synthesizer (DDS).

To solve this problem, we describe a digital phase contrast microscope that uses Zernike's phase contrast method with a hard X-ray Gabor holography associated with numerical processing and spatial frequency domain filtering techniques.

This paper presents a digital phase-locked-loop (DPLL) based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs) of MOBBPD.

This paper presents an all digital phase locked loop (ADPLL) architecture for either VLSI or low cost FPGA implementation.

To stabilize the CEO frequency in a PLL, the signal of one of the interferometers was bandpass filtered at 10.7 MHz, amplified and sent to one of the inputs of a ±32π digital phase detector (Menlo Systems).

Thus, an arbitrary digital phase modulated signal may be expressed as z ( t ) = A ∑ k = 1 N exp j 2 π f k t - k - 1 T b + φ k Π t - k - 1 T b (4).

A dynamic gain modification algorithm of a class of digital phase locked loops (DPLLs) has been proposed.

The design approach and performance of a 5-bit digital phase shifter implemented with 0.25 μm GaN HEMT technology for X-band phased arrays are described.

Similar to Appendix 1, the derivations consider a 4-symbol digital phase modulation signal that is defined in Equation (A.1).