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This paper examines crossover DPD design for MIMO applications, while using fixed-point arithmetic.
These proposed implementations are based on extensions of the discrete-time spiking neuron model, which was introduced by Soula et al., and have been implemented on Field Programmable Gate Array (FPGA) devices using fixed-point arithmetic.
Each pipeline stage is subdivided into simpler substages, resulting in over 70 substages using fixed-point arithmetic for the most part.
Furthermore, optimal speed-precision-area tradeoffs can be accomplished using fixed-point arithmetic, and custom-tailored caching architectures can be employed to alleviate bandwidth bottlenecks.
However, hardware architectures implementing these applications are designed using fixed-point arithmetic to satisfy the tight constraints on implementation area and power consumption related to embedded systems.
Vanhoucke et al. lay out several tools for creating a highly optimized CPU implementation using fixed-point arithmetic, SSE instructions, and lazy evaluation of the softmax layer [34].
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This approach uses digital computation to emulate individual neuron behavior using fixed point arithmetic operation.
A simplified version of an Evolution Strategy, using fixed point arithmetic and a hardware-friendly mutation operator, has been chosen as the search algorithm.
An alternative is to use fixed point arithmetic in which the location of the radix point within a string of digits is predetermined [24].
One of the outstanding features in our model is the aggregation of encrypted smart meter readings using fixed-point number arithmetic.
Most hardware realizations of the CORDIC algorithm employ fixed-point arithmetic, and it is certainly true in nearly all FPGA implementations.
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