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In this talk I will explain the principles underlying formal verification of discrete event systems.
Research Area: Formal verification of systems, model checking, program analysis, and automatic decision procedures for logics.
The paper presents the specification level of this architecture and a formal verification of this specification.
We illustrate such formal verification of Ptolemy II models with three case studies.
In this paper we concentrate on aspects related to modeling and formal verification of embedded systems.
This paper addresses formal verification of large integer arithmetic circuits using symbolic computer algebra techniques.
Here, we present work-in-progress on tool support for formal verification of diagrammatic models.
Section 4 discusses the formal verification of the model.
One such application area is the formal verification of hardware and software systems.
The formal verification of security protocols is an almost ideal application of automated theorem proving in industry.
Furthermore, the concise formal semantics of synchronous languages is the basis for formal verification of the correctness of the programs as well as of the used compilers [7 10].
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