A bit-width reduced FPU solves this complexity problem [5, 6].
A similar approach is shown in a bit-width optimization tool called Prcis [7].
On average the speedup of 3 was attainable through a bit-width reduction while the PSNR was maintained at acceptable level.
A bit-width reduced floating-point multiplication unit is designed using a multiplier and a hard intellectual property (IP) core in an FPGA to improve speed.
In this paper, we propose a bit-width-aware constant-delay run-time Accuracy Programmable Adder (APA) in which the probability of input combinations exhibiting accurate results is programmable and adaptively controlled by the Number of Iterations (NoIs).
Similar to fixed-point designs, we use a uniform bit width for all the variables.
Also, other signals like Clock, Chip Select (CS), MISO, and MOSI signals are connected between SDHC card and the controller through a (4 ×1) bi-directional customized multiplexer where each input line of the multiplexer is a 4 bit width data bus.
In the second step, as mentioned in Section 3.5, according to their characteristics in range and operational behavior, we can divide the variables in the design into different groups and apply a uniform bit width in each group.
Based on the range information and the internal behavior of the program, we can also try to divide the variables in the target Fortran code into several different groups, and assign a different uniform bit width for each different group.
As stated in [47], the bit width allows a maximum of 2n-1 bytos to be specified for transaction per command submitted by the user on the IPIC command interface, thus 20 bits provides 1,048,575 bytes per command.
